Silicon integrated circuits have been progressed in enlarging the scale as well as in improving the performance according to so-called Moore's rule, and supported the development of the advanced information technology (IT) society from an aspect of the hardware. This trend is expected to be continued also in future. However, it is deeply concerned that miniaturization of the conventional bulk type CMOS integrated circuit will reach its limit in near future. Its main reasons are an increase in leakage current due to the miniaturization of the transistor, a degradation in switching property of the transistor (an increase in the sub-threshold slope) and so on. In other word, a serious problem lies in that the more technology node progresses, the more percentage of ineffective power consumption due to the leakage current rather than the operating power increases.
In order to overcome this essential difficulty, the ITRS road map has declared an introduction of an ultra-thin body, fully depleted SOI (Silicon-On-Insulator) device, double-gate/multi-gate MOSFET and so on in an early stage of the decade from 2010 year. Especially, an attention has been directed towards a Fin type double gate MOSFET (FinFET) having a standing, lateral channel (Refer to Non Patent Document 1) as a promising candidate device after the 32 nm node since a fabrication process of a self-aligned double gate structure is simple.
In the conventional Fin type double gate MOS field effect transistor structure (Non Patent Document 1) shown in FIGS. 34, 35 and 36, a standing Si Fin channel 50 is sandwiched by gate materials 3 so that the potential of the channel is strongly controlled by the gate electrode arranged on both sides of the Fin channel. Therefore, such a double gate structure is effective for suppressing a leakage current between the source 7-1 and the drain 7-2. However, with miniaturization of a device size, micro fabrication of the Fin channel becomes difficult. Also with shortening of the gate length, a degradation of the sub-threshold slope due to the short channel effect becomes more serious.
In the four terminal Fin type MOS field effect transistor structure (Refer to Patent Document 1) in which gate electrodes 30-1 and 30-2 are physically separated and electrically isolated as shown in FIGS. 37, 38 and 39, gate insulator films 60-1 and 60-2 are formed at the same time on both sides of the channel so that the two gate insulator films on both sides of the channel 50 have a same thicknesses (t1=t2). This transistor can be operated by applying a fixed potential to one gate and applying a driving input signal to the other gate. By changing the fixed potential value, the threshold voltage of the transistor can certainly be controlled, but this causes a significant increase in the sub-threshold slope.
To solve this problem, a four terminal Fin type MOS field effect transistor having asymmetric thicknesses (t1<t2) of the gate insulator films 60-1 and 60-3 as shown in FIGS. 40, 41 and 42 is proposed (Refer to Patent Document 2). In this device structure, by setting the thickness of the insulator film of the controlling gate thicker than that of the insulator film of the driving gate, the problem of a significant increase in the sub-threshold slope can be solved, and at the same time the threshold voltage can be controlled.
However, for the conventional Fin type MOS field effect transistor described above, the short channel effect, difficulties in forming a narrow channel and so on according to the device miniaturization are not taken into consideration. To solve these problems, a silicon nano-wire field effect transistor such as shown in FIGS. 43, 44, 45, 46, 47 and 48 is proposed (Refer to Non Patent Document 2, 3).
Features of such a device structure include a channel having a nanometer sized circular cross-section, and a gate electrode covering all around the side surface of the channel. This structure has, therefore, a stronger controllability of the channel potential by the gate, and is more effective in suppressing the short channel effect compared with the FinFET. In addition, it gives some retardation in channel miniaturization, i.e., the dimension of the channel can be favorably larger than the gate length. However, a fabrication process thereof is extremely complicated. Furthermore, in order to increase driving current, nano-wires each having a circular cross-section have to be arranged laterally, which results in larger area penalty. Moreover, since nano-wires each having a circular cross-section are fabricated by high temperature hydrogen annealing, serious problems are still remained in uniformity, controllability, and reproducibility of the nano-wire dimension. Therefore, if a high density integrated circuit is fabricated by using such a nano-wire field effect transistor, it becomes difficult to realize a high performance, and high reliability integrated circuit due to significant variation of device characteristics on a same wafer.    Patent Document 1: Japanese Patent Application Publication No. 2002-270850.    Patent Document 2: Japanese Patent Application Publication No. 2005-167163.    Non Patent Document 1: IEEE Trans. Electron Devices, Vol. 47. No. 12, pp. 2320-2325, 2000.    Non Patent Document 2: Symposium on VLSI Technology 2004, pp. 196-197.    Non Patent Document 3: Sung Dee Suk, et al., IEDM Tech. Dig., pp. 735-738, 2005